Although most silicon integrated circuits presently use metal oxide semiconductor(MOS) field effect transistors, there are many integrated circuits made that use bipolar transistors. In particular, bipolar technologies have been developed with polysilicon emitters to minimize diffusion and reduce emitter to base capacitance, special oxidation steps to minimize the base capacitance, smaller geometries to reduce parasitic capacitance, and bonded SOI (Silicon on Insulator) wafers to minimize the collector to substrate capacitance. All of these developments fundamentally are directed toward increasing the operational speed of the bipolar device.
In order to minimize the parasitic collector resistance, a heavily doped buried layer is implanted into the silicon wafer prior to epitaxial growth. The subsequent epitaxial layer is typically doped for the intrinsic collector region and is used to form the base and emitter regions. The combination of the buffed layer and the initial silicon wafer impurity concentration determine two fundamental parasitics: the collector resistance and the collector to substrate capacitance. To minimize collector capacitance, a lightly doped substrate is required. A secondary parasitic device, namely an SCR device, is formed by multiple closely spaced transistors and leads to latch-up. This device limits the spacing between transistors. Therefore, opposing parasitics create fundamental limitation of the bipolar transistor technologies.
These basic limitations, and the elimination of latch-up, are realized with the use of bonded SOI wafers in which the individual transistor can be totally isolated by a dielectric. This is typically achieved by use of a buried oxide wafer with a refilled trench surrounding each active device.
The most common method of trench isolation, for bipolar technologies, is to etch a "moat" through the silicon to the burled oxide, oxidize the remaining silicon, deposit a thick layer of polysilicon and finally polish away the excess polysilicon from over the active area regions. This method is used because of the silicon thickness necessary to accommodate the desired 5 .mu.m heavily doped buffed layer. In CMOS technologies, where the burled layer is not utilized, it is possible to create the trench region by use of LOCOS or SWAMI field oxide methods. LOCOS and SWAMI are well known acronyms. See, for example, Semiconductor International, pp. 72-74, November 1991, for a description of an exemplary bipolar fabrication method.